In Verilog, there are two primary ways to assign values to variables inside procedural blocks: Blocking and Non-blocking.

**Blocking Assignments

Execution

• Execute sequentially within an always or initial block.
• The next statement will not execute until the current one completes.
• Order matters, as each assignment updates immediately.

Modeling

• Best for combinational logic, where outputs depend on the current inputs within the same time step.

✅ Example

always @(*) begin
    a = b + c;
    d = a * 2; // 'd' uses the updated value of 'a'
end

**Non-Blocking Assignments

Execution

• RHS expressions are evaluated immediately, but LHS updates are scheduled for the end of the current simulation time step.
• Assignments in the same block behave as if they happen in parallel.
• Later statements use the old values of variables assigned earlier in the same block.

Modeling

• Essential for sequential logic (e.g., flip-flops, registers) where updates occur on a clock edge.

✅ Example

always @(posedge clk) begin
    q <= d;
    next_q <= q; // 'next_q' gets the previous value of 'q'
end